Embodiments of the inventive concept relate generally to semiconductor technology. More particularly, embodiments of the inventive concept relate to semiconductor memory devices having additive latency.
Over the last several decades, memory devices have been continually improved to achieve higher levels of storage capacity and operating speed. These improvements have touched on nearly all aspects of the memory devices, including, for instance, their material composition, logical organization, and operating procedures.
Synchronous memory devices represent one class of memory technologies designed to improve operating speed. In synchronous memory devices, memory access operations are synchronized with an external clock signal to improve the efficiency of data access and data transfer. Over the past several years, synchronous memory devices have been enhanced in a variety of ways to improve power consumption, effective data transmission rate, and noise generation. Some of these enhancements include the introduction of double data rate synchronous memories, various data prefetch schemes, on die termination, and additive latency.
Additive latency is modification that can be used, for instance, to reduce the idle time of a memory instruction scheduler of an apparatus incorporating a synchronous memory device. Additive latency comprises an internal delay of a synchronous memory device between a time when a memory access command is received and a time when execution of a corresponding memory access operation begins. The use of the internal delay allows the memory instruction scheduler to transmit access instructions more frequently to the synchronous memory device, which can lead to improved data throughput.